Visual Tracking : CACTuS / CACTuS – FL
Visual tracking is a subfield of image processing and is the process of locating and tracking moving objects over time within video sequences. The RCL conducts research aimed at the development of innovative solutions and algorithms for the visual tracking problem with a keen focus on multi-object tracking in natural scenes without a-priori knowledge. Through its efforts the laboratory has developed the multi-object tracking algorithms Competitive Attentional Correlation Tracker using Shape (CACTuS) and a feature learning variant (CACTuS – FL). CACTuS is able to simultaneously learn the shape, behaviour and motion of a variety of different salient objects in a scene through the use of it shape estimating filters. The following video demonstrates the capabilities of CACTuS – FL.
Real-time parallel architectures based on reconfigurable computing are developed for detecting and tracking (multiple) low contrast objects in noisy and cluttered image sequences using both bio-inspired vision models and non-parametric Bayesian estimation methods.
Heterogeneous Computing Systems
Working with our visual tracking application, the CACTuS visual tracking algorithm, we have created variants of the algorithm for deployment to heterogeneous computing systems comprised of multi-core CPUs, GPU and FPGAs. During the development of these variants we have been exploring how maintaining high level algorithm structure and adopting a strict modular design impact on algorithm performance.
Operation systems for reconfigurable computing
The aim of this project was to create a multitasking environment for FPGA applications. Areas of interest are area allocation, network on a chip topologies, the interaction between network topology and area fragmentation, and the interaction between programming languages and operating systems operations. The ReconfigME OS was finished in 2008 for a single chip using simulated partial dynamic reconfiguration. The KahnME OS for networks of FPGA chips is in progress. The project looked at abstractions for the storage of application state in an environment where nodes of applications can move independently between FPGAs.
Reconfigurable computing for the simulation of infra red (IR) scenes
This project parallelised and accelerated an infrared scene simulation developed by BAE Systems through a combination of algorithm transformations and the use of a heterogeneous computer (AXEL) comprising multicore, FPGA and GPU.
A distributed operating system with hardware task mobility for reconfigurable computing on UAVs
With FPGA chips becoming more dense the need for a more flexible way to design and deploy multiple applications on single FPGAs and across a network of FPGAs is becoming apparent. This extends the work of developing an OS for sharing applications on a single chip to a network of chips. It is motivated by the needs of swarms of small UAVs where there are scenarios which require deployment of a single applications across the swarm and ability to move applications away from swarm members that might fail or need to be refuelled.
Implementation of Join Calculus Programming Abstractions on Reconfigurable Computers
Hardware Join Java as a language for specification of parallel reconfigurable computing applications. The Hardware Join Java semantics are based on the Join algebra originally proposed by Fournet. Join operational semantics are traditionally specified as a reflexive chemical abstract machine (CHAM) where the state of the system can be metaphorically represented as a “chemical soup” consisting of active definitions and running processes with potential reactions defined by a set of reduction rules. When the soup contains all the terms on the left hand side of a reduction rule the terms react and generate all the terms on the right hand side of the reduction rule removing the left hand side items. In Join Java, the reduction rule is known as a Join method with the individual terms on the left hand side called Join fragments and the entire left-hand side Join patterns. When all the fragments required to fulfil a Join pattern exist in the soup (a Pattern Matcher) the body of the Join method is executed. These Join patterns can also be viewed as guards on the message passing channel and when all the fragments of the Join pattern are called, the “guarded” message is transferred between callers of the Join fragments.
Acceleration of the simulation of Membrane computing models (Parallel P System) using FPGAs
Membrane computing investigates models of computation inspired by the features of biological cells, especially those features arising from the presence of membranes. This work explores the implementation of membrane computing models on reconfigurable hardware. Specifically, it considers strategies for the implementation of parallelism, spatial distribution and non-determinism in these models.The work has implemented the fastest membrane computer in the world (2010). A custom compiler can take a membrane model and convert it to an FPGA implementation. The implementation scales linearly in space and time up to the capacity of the FPGA. Since membrane computing models are convertible into ambient calculus type models this work is able to compute implementation these types of models as well. They are being used in computer security. Membrane computing models have the property that they can be made maximally parallel. This is achieved by using non deterministic choice in the execution of rules. This work has also shown how to implement non deterministic choice so as to achieve maximal parallelism.