Harware Join Java: A High Level Language for Specification of Reconfigurable Computing Applications
- Dr G. Stewart von Itzstein
- Pass Member -- John Hopf - Thesis
- Dr. David Kearney - Supervisor
- Dr G. Stewart von Itzstein - Associate Supervisor
Applications for reconfigurable computing are made up of a hardware component and a software component. The hardware component is loaded onto an FPGA and is usually a high-speed implementation of an algorithm specified using a Hardware Description Language such as VHDL. The software component is executed on a Microprocessor and is specified using software languages such as C++. It is responsible for controlling and managing the FPGA platform and acquiring data for processing. Irrespective of the application domain and platform being targeted, the two components always seem to be written in different languages. The communication between the two components is achieved using a combination of device driver calls on the software side and corresponding logic on the hardware side. What is desirable is a single language that allows the developer to specify both hardware and software components and abstracts away the low-level communication between them.
Developing the hardware component of a reconfigurable computing application introduces concepts unfamiliar to software developers. Concepts such as clocking which play an important role in synchronous circuits don't apply in a software context. It is therefore obvious that a software developer would find it difficult to develop accurate and useful hardware designs with tools and languages that rely on knowledge of these concepts. Ideally, a language should exist which allows the hardware developer to specify a hardware design using concepts they are familiar with. This not only applies to specifying the sequential aspects of an algorithm, but the parallel ones as well.
In addition to the specification, the other important aspect of hardware design is verification. In hardware, verification is generally achieved using simulation and although simulation is done in software, the tools and methodologies used are not the same. A common method of verification in software is to use formal methods where the behaviour of the design is modelled using a formal language and tools used to check properties. Automatic generation of formal models for the hardware components of reconfigurable applications would be useful for software developers in order to verify their specifications.
This PhD investigates the current languages, methodologies and environments for developing reconfigurable computing applications. It proposes a new language, Hardware Join Java and a compilation environment that aims to address the issues currently facing application developers. The key features are as follows:
- Single language for hardware and software component specification
- Automatic generation of all synchronisation and data communication routines on both the software and hardware side
- A high-level of abstraction (on par with Java) allowing behavioural specification of hardware
- Support for the improved concurrency specification and management introduced in Join Java
- Automatic generation of formal models of the concurrency aspect of the hardware design allowing verification using property checking tools
- Simple switching between hardware and software targeting to allow software debugging of data and control flow
- A component framework allowing the use of IP Cores (precompiled hardware solutions for commonly used algorithms)
Currently, a prototype compiler for the language has been coded using an extensible compiler. It provides basic support for all of the language features including hardware/software interface generation, formal model generation, Join Java concurrency specification and monitoring and component framework. Some basic and advanced applications have been specified using Hardware Join Java and compiled by the compiler. The compiler targets the Celoxica RC1000 development board, but in future will be ported to target further platforms such as the Tokyo Electron Devices BIOLER3 development board and a Reconfigurable Computing Operating System.